A microelectronic package in which a semiconductor die is interconnected with at least one other microelectronic component can be referred to as a “System-in-Package” or, more simply, as an “SiP.” In certain cases, it may be desirable to produce an SiP including at least one microelectronic component having a relatively large footprint. In instances wherein the SiP includes a molded body in which one or more semiconductor die have been encapsulated, the Large Footprint (LF) component can be embedded within the molded body along with the semiconductor die. Such an approach, however, results in a significant increase in the overall planform dimensions of the SiP, which may be unacceptable in certain applications. This increase in SiP planform dimensions can be minimized by mounting the LF component to the package frontside or backside in a stacked or three dimensional arrangement. However, rarely is there provided sufficient area on the package frontside to accommodate one or more LF components due to, for example, the presence of a Ball Grid Array (BGA) or other frontside contact array. Conversely, mounting the LF component to the package backside can introduce undesired cost and complexity to manufacturing process in instances wherein interconnection of the LF component requires build-up of one or more Redistribution Layers (RDLs) over the package backside or the formation of one or more Through Package Vias (TPVs) through the package body.
It would thus be desirable to provide SIPs and methods for fabricating SiPs enabling microelectronic components having relatively large footprints to be integrated into a given SiP, while minimizing the planform dimensions thereof. It would also be desirable for such an SiP fabrication method to be relatively straightforward and cost effective to implement. Other desirable features and characteristics of the present invention will become apparent from the subsequent Detailed Description and the appended Claims, taken in conjunction with the accompanying Drawings and the foregoing Background.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the invention described in the subsequent Detailed Description. It should further be understood that features or elements appearing in the accompanying figures are not necessarily drawn to scale unless otherwise stated. For example, the dimensions of certain elements or regions in the figures may be exaggerated relative to other elements or regions to improve understanding of embodiments of the invention.